29 #define QQQdialect MPLABX 43 #undef QQQMULTIPROCESSEXH 46 #define qqqMaxBranchDepth 20 47 #define QQQstructbitmap 59 #undef QQQTEMPLATEONLY 61 #define QQQUPLOADATEND 63 #undef QQQASHLINGVITRA 65 #define qqqbitmapint unsigned int 67 #undef QQQTIC2XSERIALIO 69 #undef QQQCOMPRESSED_EXH 76 #define hvps_61zzopen zzopen 78 #define hvps_61zqqzqz1 zqqzqz1 81 #define FILEPOINT FILE * f, 82 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 98 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 102 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 111 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 112 #ifndef LDRA_VOID_FUNC 113 #define LDRA_VOID_FUNC 116 #if defined(QQQMAINFL) 139 #ifdef QQQ_KEEPCOMMENTS 147 #if !defined(QQQSUPPRESS_UNDEF) 153 #undef QQQHITMAP_STORAGE 155 #define qqnull_params void 156 #define QQQ_PROTOTYPE_DEF 158 #undef QQ_ANSI_PROTOTYPE 160 #define QQ_ANSI_PROTOTYPE 1 163 #define QQ_ANSI_PROTOTYPE 1 169 #define ELEMENT(N) qqqbitmapint element##N; 171 #include "hvps_61zbelem.def" 175 #define ELEMENT(N) 0, 177 #include "hvps_61zbelem.def" 247 #ifndef _SYS_DEFINITIONS_H 248 #define _SYS_DEFINITIONS_H 257 #include "system/common/sys_common.h" 258 #include "system/common/sys_module.h" 342 #ifndef _SYSTEM_CONFIG_H 343 #define _SYSTEM_CONFIG_H 362 #define SYS_VERSION_STR "2.06" 363 #define SYS_VERSION 20600 367 #define SYS_CLK_FREQ 200000000ul 368 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 369 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 370 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 371 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 372 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 373 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 374 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 375 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 376 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 378 #define SYS_PORT_A_ANSEL 0x3F00 379 #define SYS_PORT_A_TRIS 0xFFED 380 #define SYS_PORT_A_LAT 0x0010 381 #define SYS_PORT_A_ODC 0x0000 382 #define SYS_PORT_A_CNPU 0x0020 383 #define SYS_PORT_A_CNPD 0x0000 384 #define SYS_PORT_A_CNEN 0x0021 385 #define SYS_PORT_B_ANSEL 0x10C8 386 #define SYS_PORT_B_TRIS 0x91FF 387 #define SYS_PORT_B_LAT 0x0000 388 #define SYS_PORT_B_ODC 0x0000 389 #define SYS_PORT_B_CNPU 0x0000 390 #define SYS_PORT_B_CNPD 0x0000 391 #define SYS_PORT_B_CNEN 0x0000 392 #define SYS_PORT_C_ANSEL 0xCFE1 393 #define SYS_PORT_C_TRIS 0xFFFF 394 #define SYS_PORT_C_LAT 0x0000 395 #define SYS_PORT_C_ODC 0x0000 396 #define SYS_PORT_C_CNPU 0x0000 397 #define SYS_PORT_C_CNPD 0x0000 398 #define SYS_PORT_C_CNEN 0x0000 399 #define SYS_PORT_D_ANSEL 0xC100 400 #define SYS_PORT_D_TRIS 0xFFFF 401 #define SYS_PORT_D_LAT 0x0000 402 #define SYS_PORT_D_ODC 0x0000 403 #define SYS_PORT_D_CNPU 0x0000 404 #define SYS_PORT_D_CNPD 0x0000 405 #define SYS_PORT_D_CNEN 0x0000 406 #define SYS_PORT_E_ANSEL 0xFC00 407 #define SYS_PORT_E_TRIS 0xFDFF 408 #define SYS_PORT_E_LAT 0x0000 409 #define SYS_PORT_E_ODC 0x0000 410 #define SYS_PORT_E_CNPU 0x0000 411 #define SYS_PORT_E_CNPD 0x0000 412 #define SYS_PORT_E_CNEN 0x0000 413 #define SYS_PORT_F_ANSEL 0xCEC0 414 #define SYS_PORT_F_TRIS 0xEFFF 415 #define SYS_PORT_F_LAT 0x0000 416 #define SYS_PORT_F_ODC 0x0000 417 #define SYS_PORT_F_CNPU 0x0000 418 #define SYS_PORT_F_CNPD 0x0000 419 #define SYS_PORT_F_CNEN 0x0000 420 #define SYS_PORT_G_ANSEL 0x8CBC 421 #define SYS_PORT_G_TRIS 0xDFFF 422 #define SYS_PORT_G_LAT 0x0000 423 #define SYS_PORT_G_ODC 0x0000 424 #define SYS_PORT_G_CNPU 0x0000 425 #define SYS_PORT_G_CNPD 0x0000 426 #define SYS_PORT_G_CNEN 0x0000 427 #define SYS_PORT_H_ANSEL 0x0070 428 #define SYS_PORT_H_TRIS 0xB3FB 429 #define SYS_PORT_H_LAT 0x0000 430 #define SYS_PORT_H_ODC 0x0000 431 #define SYS_PORT_H_CNPU 0x0000 432 #define SYS_PORT_H_CNPD 0x0000 433 #define SYS_PORT_H_CNEN 0x0000 434 #define SYS_PORT_J_ANSEL 0x0000 435 #define SYS_PORT_J_TRIS 0x8B7F 436 #define SYS_PORT_J_LAT 0x0080 437 #define SYS_PORT_J_ODC 0x0000 438 #define SYS_PORT_J_CNPU 0x0000 439 #define SYS_PORT_J_CNPD 0x0000 440 #define SYS_PORT_J_CNEN 0x0800 441 #define SYS_PORT_K_ANSEL 0xFF00 442 #define SYS_PORT_K_TRIS 0xFFFF 443 #define SYS_PORT_K_LAT 0x0000 444 #define SYS_PORT_K_ODC 0x0000 445 #define SYS_PORT_K_CNPU 0x0000 446 #define SYS_PORT_K_CNPD 0x0000 447 #define SYS_PORT_K_CNEN 0x0000 451 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 452 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 453 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 454 #define SYS_TMR_FREQUENCY 1000 455 #define SYS_TMR_FREQUENCY_TOLERANCE 10 456 #define SYS_TMR_UNIT_RESOLUTION 10000 457 #define SYS_TMR_CLIENT_TOLERANCE 10 458 #define SYS_TMR_INTERRUPT_NOTIFICATION false 464 #define DRV_IC_DRIVER_MODE_STATIC 467 #define DRV_SPI_NUMBER_OF_MODULES 6 470 #define DRV_SPI_POLLED 1 471 #define DRV_SPI_ISR 0 472 #define DRV_SPI_MASTER 1 473 #define DRV_SPI_SLAVE 0 475 #define DRV_SPI_EBM 1 476 #define DRV_SPI_8BIT 1 477 #define DRV_SPI_16BIT 1 478 #define DRV_SPI_32BIT 0 479 #define DRV_SPI_DMA 0 481 #define DRV_SPI_INSTANCES_NUMBER 3 482 #define DRV_SPI_CLIENTS_NUMBER 3 483 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 485 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 486 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 487 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 488 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 489 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 490 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 491 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 492 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 493 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 494 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 495 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 496 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 497 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 498 #define DRV_SPI_BAUD_RATE_IDX0 1000000 499 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 500 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 501 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 502 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 503 #define DRV_SPI_QUEUE_SIZE_IDX0 10 504 #define DRV_SPI_RESERVED_JOB_IDX0 1 506 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 507 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 508 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 509 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 510 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 511 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 512 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 513 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 514 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 515 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 516 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 517 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 518 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 519 #define DRV_SPI_BAUD_RATE_IDX1 1000000 520 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 521 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 522 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 523 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 524 #define DRV_SPI_QUEUE_SIZE_IDX1 10 525 #define DRV_SPI_RESERVED_JOB_IDX1 1 527 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 528 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 529 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 530 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 531 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 532 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 533 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 534 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 535 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 536 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 537 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 538 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 539 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 540 #define DRV_SPI_BAUD_RATE_IDX2 500000 541 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 542 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 543 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 544 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 545 #define DRV_SPI_QUEUE_SIZE_IDX2 10 546 #define DRV_SPI_RESERVED_JOB_IDX2 1 548 #define DRV_TMR_INTERRUPT_MODE true 550 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 551 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 552 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 553 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 554 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 555 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 556 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 557 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 558 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 559 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 560 #define DRV_TMR_POWER_STATE_IDX0 561 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 562 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 563 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 564 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 565 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 566 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 567 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 568 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 569 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 570 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 571 #define DRV_TMR_POWER_STATE_IDX1 573 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 574 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 575 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 576 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 577 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 578 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 579 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 580 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 581 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 582 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 583 #define DRV_TMR_POWER_STATE_IDX2 585 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 586 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 587 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 588 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 589 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 590 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 591 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 592 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 593 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 594 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 595 #define DRV_TMR_POWER_STATE_IDX3 597 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 598 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 599 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 600 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 601 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 602 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 603 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 604 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 605 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 606 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 607 #define DRV_TMR_POWER_STATE_IDX4 611 #define DRV_USART_INSTANCES_NUMBER 1 612 #define DRV_USART_CLIENTS_NUMBER 1 613 #define DRV_USART_INTERRUPT_MODE false 614 #define DRV_USART_BYTE_MODEL_SUPPORT true 615 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 616 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 624 #define DRV_USBHS_DEVICE_SUPPORT true 626 #define DRV_USBHS_HOST_SUPPORT false 628 #define DRV_USBHS_INSTANCES_NUMBER 1 630 #define DRV_USBHS_INTERRUPT_MODE true 632 #define DRV_USBHS_ENDPOINTS_NUMBER 2 635 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 637 #define USB_DEVICE_INSTANCES_NUMBER 1 639 #define USB_DEVICE_EP0_BUFFER_SIZE 64 641 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 649 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 650 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 651 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 652 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 653 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 655 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 656 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 657 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 658 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 659 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 661 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 662 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 663 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 664 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 665 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 667 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 668 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 669 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 670 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 671 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 673 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 674 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 675 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 676 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 677 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 679 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 680 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 681 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 682 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 683 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 685 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 686 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 687 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 688 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 689 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 691 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 692 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 693 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 694 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 695 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 697 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 698 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 699 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 700 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 701 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 703 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 704 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 705 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 706 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 707 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 709 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 710 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 711 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 712 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 713 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 715 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 716 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 717 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 718 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 719 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 721 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 722 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 723 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 724 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 725 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 727 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 728 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 729 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 730 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 731 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 733 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 734 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 735 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 736 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 737 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 739 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 740 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 741 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 742 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 743 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 745 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 746 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 747 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 748 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 749 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 751 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 752 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 753 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 754 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 755 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 757 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 758 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 759 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 760 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 761 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 763 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 765 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 767 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 769 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 771 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 773 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 775 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 777 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 779 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 781 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 783 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 785 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 787 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 789 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 791 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 793 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 795 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 796 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 797 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 798 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 799 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 800 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 801 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 850 #ifndef _DRV_COMMON_H 851 #define _DRV_COMMON_H 953 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 963 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 973 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1029 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1040 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1055 #define _PLIB_UNSUPPORTED 1063 #include "system/common/sys_module.h" 1075 #define DRV_IC_INDEX_0 0 1076 #define DRV_IC_INDEX_1 1 1077 #define DRV_IC_INDEX_2 2 1078 #define DRV_IC_INDEX_3 3 1079 #define DRV_IC_INDEX_4 4 1080 #define DRV_IC_INDEX_5 5 1081 #define DRV_IC_INDEX_6 6 1082 #define DRV_IC_INDEX_7 7 1083 #define DRV_IC_INDEX_8 8 1084 #define DRV_IC_INDEX_9 9 1085 #define DRV_IC_INDEX_10 10 1086 #define DRV_IC_INDEX_11 11 1087 #define DRV_IC_INDEX_12 12 1088 #define DRV_IC_INDEX_13 13 1089 #define DRV_IC_INDEX_14 14 1090 #define DRV_IC_INDEX_15 15 1122 const SYS_MODULE_INDEX index ,
1123 const SYS_MODULE_INIT *
const init ) ;
1145 const SYS_MODULE_INDEX drvIndex ,
1190 const SYS_MODULE_INDEX drvIndex ,
1323 #ifndef _DRV_IC_STATIC_H 1324 #define _DRV_IC_STATIC_H 1325 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1326 #define DRV_IC_Close( handle ) 1365 #include "system/devcon/sys_devcon.h" 1366 #include "system/clk/sys_clk.h" 1367 #include "system/int/sys_int.h" 1368 #include "system/tmr/sys_tmr.h" 1410 #ifndef _DRV_ADC_STATIC_H 1411 #define _DRV_ADC_STATIC_H 1412 #include <stdbool.h> 1413 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1414 #include "peripheral/adchs/plib_adchs.h" 1415 #include "peripheral/int/plib_int.h" 1455 uint8_t bufIndex ) ;
1459 uint8_t bufIndex ) ;
1509 #ifndef _DRV_TMR_STATIC_H 1510 #define _DRV_TMR_STATIC_H 1559 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1560 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1561 #include "peripheral/tmr/plib_tmr.h" 1597 #ifndef _TMR_DEFINITIONS_PIC32M_H 1598 #define _TMR_DEFINITIONS_PIC32M_H 1656 #include "system/int/sys_int.h" 1657 #include "system/clk/sys_clk.h" 1676 #define DRV_TMR_INDEX_0 0 1677 #define DRV_TMR_INDEX_1 1 1678 #define DRV_TMR_INDEX_2 2 1679 #define DRV_TMR_INDEX_3 3 1680 #define DRV_TMR_INDEX_4 4 1681 #define DRV_TMR_INDEX_5 5 1682 #define DRV_TMR_INDEX_6 6 1683 #define DRV_TMR_INDEX_7 7 1684 #define DRV_TMR_INDEX_8 8 1685 #define DRV_TMR_INDEX_9 9 1686 #define DRV_TMR_INDEX_10 10 1687 #define DRV_TMR_INDEX_11 11 1698 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1783 uint32_t dividerMin ;
1785 uint32_t dividerMax ;
1788 uint32_t dividerStep ;
1804 SYS_MODULE_INIT moduleInit ;
1806 TMR_MODULE_ID tmrId ;
1810 TMR_PRESCALE prescale ;
1814 INT_SOURCE interruptSource ;
1822 bool asyncWriteEnable ;
1837 uint32_t alarmCount ) ;
1899 const SYS_MODULE_INDEX drvIndex ,
1900 const SYS_MODULE_INIT *
const init ) ;
1940 SYS_MODULE_OBJ
object ) ;
1987 SYS_MODULE_OBJ
object ) ;
2021 SYS_MODULE_OBJ
object ) ;
2075 const SYS_MODULE_INDEX index ,
2176 uint32_t counterPeriod ) ;
2666 TMR_PRESCALE preScale ) ;
2906 #ifndef _DRV_TMR_DEPRECATED_H 2907 #define _DRV_TMR_DEPRECATED_H 2948 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3012 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3077 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3136 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3197 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3256 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3317 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3347 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3379 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3410 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3442 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3504 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3569 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3586 #include "peripheral/tmr/plib_tmr.h" 3587 #include "peripheral/int/plib_int.h" 3589 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3591 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3593 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3595 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3614 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3620 static inline SYS_STATUS
3623 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3634 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3645 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3655 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3664 TMR_PRESCALE prescale ) ;
3695 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3724 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3730 static inline SYS_STATUS
3733 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3744 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3755 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3765 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3774 TMR_PRESCALE prescale ) ;
3805 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3834 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3840 static inline SYS_STATUS
3843 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3854 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3865 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3875 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3884 TMR_PRESCALE prescale ) ;
3915 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3944 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3950 static inline SYS_STATUS
3953 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3964 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3975 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3985 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
3994 TMR_PRESCALE prescale ) ;
4025 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4054 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4060 static inline SYS_STATUS
4063 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4074 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4085 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4095 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4104 TMR_PRESCALE prescale ) ;
4135 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4154 #include "peripheral/int/plib_int.h" 4196 #ifndef _DRV_PMP_STATIC_H 4197 #define _DRV_PMP_STATIC_H 4198 #include "peripheral/pmp/plib_pmp.h" 4213 PMP_DATA_WAIT_STATES dataWait ,
4214 PMP_STROBE_WAIT_STATES strobeWait ,
4215 PMP_DATA_HOLD_STATES dataHold ) ;
4270 #ifndef _DRV_USART_STATIC_H 4271 #define _DRV_USART_STATIC_H 4310 #ifndef _DRV_USART_STATIC_LOCAL_H 4311 #define _DRV_USART_STATIC_LOCAL_H 4318 #include <stdbool.h> 4355 #ifndef _DRV_USART_H 4356 #define _DRV_USART_H 4396 #ifndef _DRV_USART_DEFINITIONS_H 4397 #define _DRV_USART_DEFINITIONS_H 4403 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4404 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4441 #ifndef _PLIB_USART_H 4442 #define _PLIB_USART_H 4485 #ifndef _USART_PROCESSOR_H 4486 #define _USART_PROCESSOR_H 4495 #include <stdbool.h> 4496 #error "No Processor Family specified" 4540 USART_MODULE_ID index ) ;
4570 USART_MODULE_ID index ) ;
4602 USART_MODULE_ID index ) ;
4636 USART_MODULE_ID index ,
4637 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4666 USART_BRG_CLOCK_SOURCE
4668 USART_MODULE_ID index ) ;
4722 USART_MODULE_ID index ) ;
4752 USART_MODULE_ID index ) ;
4781 USART_MODULE_ID index ) ;
4813 USART_MODULE_ID index ) ;
4844 USART_MODULE_ID index ) ;
4886 USART_MODULE_ID index ) ;
4919 USART_MODULE_ID index ) ;
4951 USART_MODULE_ID index ) ;
4992 USART_MODULE_ID index ,
4993 uint32_t clockFrequency ,
4994 uint32_t baudRate ) ;
5035 USART_MODULE_ID index ,
5036 uint32_t clockFrequency ,
5037 uint32_t baudRate ) ;
5070 USART_MODULE_ID index ,
5071 int32_t clockFrequency ) ;
5106 USART_MODULE_ID index ,
5141 USART_MODULE_ID index ) ;
5176 USART_MODULE_ID index ,
5211 USART_MODULE_ID index ) ;
5243 USART_MODULE_ID index ) ;
5277 USART_MODULE_ID index ) ;
5310 USART_MODULE_ID index ) ;
5343 USART_MODULE_ID index ) ;
5377 USART_MODULE_ID index ,
5422 USART_MODULE_ID index ) ;
5456 USART_MODULE_ID index ) ;
5492 USART_MODULE_ID index ) ;
5529 USART_MODULE_ID index ,
5569 USART_MODULE_ID index ) ;
5607 USART_MODULE_ID index ) ;
5642 USART_MODULE_ID index ) ;
5676 USART_MODULE_ID index ) ;
5710 USART_MODULE_ID index ) ;
5743 USART_MODULE_ID index ) ;
5775 USART_MODULE_ID index ) ;
5807 USART_MODULE_ID index ) ;
5840 USART_MODULE_ID index ) ;
5874 USART_MODULE_ID index ) ;
5903 USART_MODULE_ID index ) ;
5932 USART_MODULE_ID index ) ;
5964 USART_MODULE_ID index ) ;
5996 USART_MODULE_ID index ) ;
6026 USART_MODULE_ID index ) ;
6056 USART_MODULE_ID index ) ;
6085 USART_MODULE_ID index ) ;
6114 USART_MODULE_ID index ) ;
6148 USART_MODULE_ID index ,
6149 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6181 USART_MODULE_ID index ,
6182 USART_RECEIVE_INTR_MODE interruptMode ) ;
6215 USART_MODULE_ID index ,
6216 USART_LINECONTROL_MODE dataFlowConfig ) ;
6249 USART_MODULE_ID index ,
6250 USART_HANDSHAKE_MODE handshakeConfig ) ;
6283 USART_MODULE_ID index ,
6314 USART_MODULE_ID index ) ;
6343 USART_MODULE_ID index ) ;
6374 USART_MODULE_ID index ) ;
6405 USART_MODULE_ID index ) ;
6435 USART_MODULE_ID index ) ;
6467 USART_MODULE_ID index ,
6468 USART_OPERATION_MODE operationmode ) ;
6498 USART_MODULE_ID index ) ;
6531 USART_MODULE_ID index ) ;
6560 USART_MODULE_ID index ) ;
6590 USART_MODULE_ID index ) ;
6626 USART_MODULE_ID index ) ;
6677 USART_MODULE_ID index ,
6680 bool wakeFromSleep ,
6725 USART_MODULE_ID index ,
6726 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6727 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6728 USART_OPERATION_MODE operationMode ) ;
6774 USART_MODULE_ID index ,
6775 uint32_t systemClock ,
6821 USART_MODULE_ID index ) ;
6842 USART_MODULE_ID index ) ;
6863 USART_MODULE_ID index ) ;
6897 USART_MODULE_ID index ) ;
6924 USART_MODULE_ID index ) ;
6950 USART_MODULE_ID index ) ;
6977 USART_MODULE_ID index ) ;
7003 USART_MODULE_ID index ) ;
7028 USART_MODULE_ID index ) ;
7054 USART_MODULE_ID index ) ;
7079 USART_MODULE_ID index ) ;
7105 USART_MODULE_ID index ) ;
7130 USART_MODULE_ID index ) ;
7156 USART_MODULE_ID index ) ;
7183 USART_MODULE_ID index ) ;
7209 USART_MODULE_ID index ) ;
7235 USART_MODULE_ID index ) ;
7262 USART_MODULE_ID index ) ;
7289 USART_MODULE_ID index ) ;
7316 USART_MODULE_ID index ) ;
7342 USART_MODULE_ID index ) ;
7367 USART_MODULE_ID index ) ;
7393 USART_MODULE_ID index ) ;
7420 USART_MODULE_ID index ) ;
7446 USART_MODULE_ID index ) ;
7472 USART_MODULE_ID index ) ;
7497 USART_MODULE_ID index ) ;
7522 USART_MODULE_ID index ) ;
7547 USART_MODULE_ID index ) ;
7573 USART_MODULE_ID index ) ;
7598 USART_MODULE_ID index ) ;
7624 USART_MODULE_ID index ) ;
7650 USART_MODULE_ID index ) ;
7675 USART_MODULE_ID index ) ;
7701 USART_MODULE_ID index ) ;
7726 USART_MODULE_ID index ) ;
7751 USART_MODULE_ID index ) ;
7778 USART_MODULE_ID index ) ;
7803 USART_MODULE_ID index ) ;
7829 USART_MODULE_ID index ) ;
7894 #include "system/common/sys_common.h" 7895 #include "system/common/sys_module.h" 7907 #include "system/int/sys_int.h" 7979 #ifndef _SYS_DMA_DEFINITIONS_H 7980 #define _SYS_DMA_DEFINITIONS_H 7986 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7987 #include "system/common/sys_common.h" 7988 #include "system/common/sys_module.h" 8058 #ifndef _PLIB_DMA_PROCESSOR_H 8059 #define _PLIB_DMA_PROCESSOR_H 8060 #error "Can't find header" 8104 DMA_MODULE_ID index ,
8105 DMA_CHANNEL channel ) ;
8139 DMA_MODULE_ID index ,
8140 DMA_CHANNEL channel ,
8141 DMA_CHANNEL_COLLISION collisonType ) ;
8173 DMA_MODULE_ID index ,
8174 DMA_CHANNEL channel ) ;
8206 DMA_MODULE_ID index ,
8207 DMA_CHANNEL channel ) ;
8245 DMA_MODULE_ID index ,
8246 DMA_CHANNEL channel ,
8247 DMA_CHANNEL_PRIORITY channelPriority ) ;
8276 DMA_CHANNEL_PRIORITY
8278 DMA_MODULE_ID index ,
8279 DMA_CHANNEL channel ) ;
8307 DMA_MODULE_ID index ,
8308 DMA_CHANNEL_PRIORITY channelPriority ) ;
8333 DMA_CHANNEL_PRIORITY
8335 DMA_MODULE_ID index ) ;
8365 DMA_MODULE_ID index ,
8366 DMA_CHANNEL channel ) ;
8397 DMA_MODULE_ID index ,
8398 DMA_CHANNEL channel ) ;
8427 DMA_MODULE_ID index ,
8428 DMA_CHANNEL channel ) ;
8457 DMA_MODULE_ID index ,
8458 DMA_CHANNEL channel ) ;
8489 DMA_MODULE_ID index ,
8490 DMA_CHANNEL channel ) ;
8519 DMA_MODULE_ID index ,
8520 DMA_CHANNEL channel ) ;
8551 DMA_MODULE_ID index ,
8552 DMA_CHANNEL channel ) ;
8583 DMA_MODULE_ID index ,
8584 DMA_CHANNEL channel ) ;
8613 DMA_MODULE_ID index ,
8614 DMA_CHANNEL channel ) ;
8645 DMA_MODULE_ID index ,
8646 DMA_CHANNEL channel ) ;
8675 DMA_MODULE_ID index ,
8676 DMA_CHANNEL channel ) ;
8706 DMA_MODULE_ID index ,
8707 DMA_CHANNEL channel ) ;
8737 DMA_MODULE_ID index ,
8738 DMA_CHANNEL channel ) ;
8768 DMA_MODULE_ID index ,
8769 DMA_CHANNEL channel ) ;
8799 DMA_MODULE_ID index ,
8800 DMA_CHANNEL channel ) ;
8831 DMA_MODULE_ID index ,
8832 DMA_CHANNEL channel ) ;
8863 DMA_MODULE_ID index ,
8864 DMA_CHANNEL channel ,
8865 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8894 DMA_CHANNEL_TRANSFER_DIRECTION
8896 DMA_MODULE_ID index ,
8897 DMA_CHANNEL channel ) ;
8933 DMA_MODULE_ID index ,
8934 DMA_CHANNEL channel ,
8936 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8969 DMA_MODULE_ID index ,
8970 DMA_CHANNEL channel ,
8971 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9002 DMA_MODULE_ID index ,
9003 DMA_CHANNEL channel ,
9004 uint16_t peripheraladdress ) ;
9032 DMA_MODULE_ID index ,
9033 DMA_CHANNEL channel ) ;
9064 DMA_MODULE_ID index ,
9065 DMA_CHANNEL channel ,
9066 uint16_t transferCount ) ;
9094 DMA_MODULE_ID index ,
9095 DMA_CHANNEL channel ) ;
9128 DMA_MODULE_ID index ,
9129 DMA_CHANNEL channel ,
9130 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9158 DMA_SOURCE_ADDRESSING_MODE
9160 DMA_MODULE_ID index ,
9161 DMA_CHANNEL channel ) ;
9194 DMA_MODULE_ID index ,
9195 DMA_CHANNEL channel ,
9196 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9225 DMA_DESTINATION_ADDRESSING_MODE
9227 DMA_MODULE_ID index ,
9228 DMA_CHANNEL channel ) ;
9261 DMA_MODULE_ID index ,
9262 DMA_CHANNEL channel ,
9263 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9291 DMA_CHANNEL_ADDRESSING_MODE
9293 DMA_MODULE_ID index ,
9294 DMA_CHANNEL channel ) ;
9332 DMA_MODULE_ID index ,
9333 DMA_CHANNEL channel ,
9334 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9370 DMA_MODULE_ID index ,
9371 DMA_CHANNEL channel ,
9372 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9407 DMA_MODULE_ID index ,
9408 DMA_CHANNEL channel ,
9409 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9438 DMA_CHANNEL_INT_SOURCE
9440 DMA_MODULE_ID index ,
9441 DMA_CHANNEL channel ) ;
9476 DMA_MODULE_ID index ,
9477 DMA_CHANNEL channel ,
9478 DMA_TRIGGER_SOURCE IRQnum ) ;
9513 DMA_MODULE_ID index ,
9514 DMA_CHANNEL channel ,
9515 DMA_TRIGGER_SOURCE IRQ ) ;
9546 DMA_MODULE_ID index ,
9547 DMA_CHANNEL channel ,
9548 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9575 DMA_CHANNEL_DATA_SIZE
9577 DMA_MODULE_ID index ,
9578 DMA_CHANNEL channel ) ;
9612 DMA_MODULE_ID index ,
9613 DMA_CHANNEL channel ,
9614 DMA_TRANSFER_MODE channeltransferMode ) ;
9646 DMA_MODULE_ID index ,
9647 DMA_CHANNEL channel ) ;
9676 DMA_MODULE_ID index ,
9677 DMA_CHANNEL channel ) ;
9707 DMA_MODULE_ID index ,
9708 DMA_CHANNEL channel ) ;
9737 DMA_MODULE_ID index ,
9738 DMA_CHANNEL channel ) ;
9766 DMA_MODULE_ID index ,
9767 DMA_CHANNEL channel ) ;
9797 DMA_MODULE_ID index ,
9798 DMA_CHANNEL channel ) ;
9825 DMA_MODULE_ID index ,
9826 DMA_CHANNEL channel ) ;
9862 DMA_MODULE_ID index ,
9863 DMA_CHANNEL channel ) ;
9894 DMA_MODULE_ID index ,
9895 DMA_CHANNEL channel ) ;
9928 DMA_MODULE_ID index ) ;
9957 DMA_MODULE_ID index ) ;
9987 DMA_MODULE_ID index ) ;
10016 DMA_MODULE_ID index ) ;
10045 DMA_MODULE_ID index ) ;
10075 DMA_MODULE_ID index ) ;
10103 DMA_MODULE_ID index ) ;
10131 DMA_MODULE_ID index ) ;
10159 DMA_MODULE_ID index ) ;
10188 DMA_MODULE_ID index ) ;
10216 DMA_MODULE_ID index ) ;
10250 DMA_MODULE_ID index ) ;
10280 DMA_MODULE_ID index ) ;
10310 DMA_MODULE_ID index ) ;
10339 DMA_MODULE_ID index ) ;
10374 DMA_MODULE_ID index ,
10375 DMA_CHANNEL channel ) ;
10404 DMA_MODULE_ID index ) ;
10436 DMA_MODULE_ID index ,
10437 DMA_CRC_TYPE CRCType ) ;
10468 DMA_MODULE_ID index ) ;
10498 DMA_MODULE_ID index ) ;
10528 DMA_MODULE_ID index ) ;
10558 DMA_MODULE_ID index ) ;
10587 DMA_MODULE_ID index ) ;
10617 DMA_MODULE_ID index ) ;
10646 DMA_MODULE_ID index ) ;
10676 DMA_MODULE_ID index ,
10677 uint8_t polyLength ) ;
10706 DMA_MODULE_ID index ) ;
10735 DMA_MODULE_ID index ,
10736 DMA_CRC_BIT_ORDER bitOrder ) ;
10767 DMA_MODULE_ID index ) ;
10796 DMA_MODULE_ID index ) ;
10826 DMA_MODULE_ID index ,
10827 DMA_CRC_BYTE_ORDER byteOrder ) ;
10856 DMA_MODULE_ID index ) ;
10887 DMA_MODULE_ID index ) ;
10919 DMA_MODULE_ID index ,
10920 uint32_t DMACRCdata ) ;
10951 DMA_MODULE_ID index ) ;
10984 DMA_MODULE_ID index ,
10985 uint32_t DMACRCXOREnableMask ) ;
11023 DMA_MODULE_ID index ,
11024 DMA_CHANNEL dmaChannel ) ;
11061 DMA_MODULE_ID index ,
11062 DMA_CHANNEL dmaChannel ,
11063 uint32_t sourceStartAddress ) ;
11097 DMA_MODULE_ID index ,
11098 DMA_CHANNEL dmaChannel ) ;
11136 DMA_MODULE_ID index ,
11137 DMA_CHANNEL dmaChannel ,
11138 uint32_t destinationStartAddress ) ;
11178 DMA_MODULE_ID index ,
11179 DMA_CHANNEL dmaChannel ) ;
11218 DMA_MODULE_ID index ,
11219 DMA_CHANNEL dmaChannel ,
11220 uint16_t sourceSize ) ;
11255 DMA_MODULE_ID index ,
11256 DMA_CHANNEL dmaChannel ) ;
11293 DMA_MODULE_ID index ,
11294 DMA_CHANNEL dmaChannel ,
11295 uint16_t destinationSize ) ;
11329 DMA_MODULE_ID index ,
11330 DMA_CHANNEL dmaChannel ) ;
11365 DMA_MODULE_ID index ,
11366 DMA_CHANNEL dmaChannel ) ;
11401 DMA_MODULE_ID index ,
11402 DMA_CHANNEL dmaChannel ) ;
11439 DMA_MODULE_ID index ,
11440 DMA_CHANNEL dmaChannel ,
11441 uint16_t CellSize ) ;
11475 DMA_MODULE_ID index ,
11476 DMA_CHANNEL dmaChannel ) ;
11513 DMA_MODULE_ID index ,
11514 DMA_CHANNEL dmaChannel ) ;
11553 DMA_MODULE_ID index ,
11554 DMA_CHANNEL dmaChannel ,
11555 uint16_t patternData ) ;
11599 DMA_MODULE_ID index ,
11600 DMA_CHANNEL dmaChannel ,
11601 DMA_INT_TYPE dmaINTSource ) ;
11636 DMA_MODULE_ID index ,
11637 DMA_CHANNEL dmaChannel ,
11638 DMA_INT_TYPE dmaINTSource ) ;
11674 DMA_MODULE_ID index ,
11675 DMA_CHANNEL dmaChannel ,
11676 DMA_INT_TYPE dmaINTSource ) ;
11710 DMA_MODULE_ID index ,
11711 DMA_CHANNEL dmaChannel ,
11712 DMA_INT_TYPE dmaINTSource ) ;
11746 DMA_MODULE_ID index ,
11747 DMA_CHANNEL dmaChannel ,
11748 DMA_INT_TYPE dmaINTSource ) ;
11786 DMA_MODULE_ID index ,
11787 DMA_CHANNEL dmaChannel ,
11788 DMA_INT_TYPE dmaINTSource ) ;
11821 DMA_MODULE_ID index ,
11822 DMA_CHANNEL dmaChannel ,
11823 DMA_PATTERN_LENGTH patternLen ) ;
11856 DMA_MODULE_ID index ,
11857 DMA_CHANNEL dmaChannel ) ;
11887 DMA_MODULE_ID index ,
11888 DMA_CHANNEL channel ) ;
11921 DMA_MODULE_ID index ,
11922 DMA_CHANNEL channel ) ;
11952 DMA_MODULE_ID index ,
11953 DMA_CHANNEL channel ) ;
11985 DMA_MODULE_ID index ,
11986 DMA_CHANNEL channel ,
11987 uint8_t pattern ) ;
12018 DMA_MODULE_ID index ,
12019 DMA_CHANNEL channel ) ;
12051 DMA_MODULE_ID index ) ;
12076 DMA_MODULE_ID index ) ;
12100 DMA_MODULE_ID index ) ;
12125 DMA_MODULE_ID index ) ;
12148 DMA_MODULE_ID index ) ;
12172 DMA_MODULE_ID index ) ;
12195 DMA_MODULE_ID index ) ;
12219 DMA_MODULE_ID index ) ;
12243 DMA_MODULE_ID index ) ;
12268 DMA_MODULE_ID index ) ;
12292 DMA_MODULE_ID index ) ;
12316 DMA_MODULE_ID index ) ;
12339 DMA_MODULE_ID index ) ;
12363 DMA_MODULE_ID index ) ;
12387 DMA_MODULE_ID index ) ;
12411 DMA_MODULE_ID index ) ;
12435 DMA_MODULE_ID index ) ;
12459 DMA_MODULE_ID index ) ;
12482 DMA_MODULE_ID index ) ;
12507 DMA_MODULE_ID index ) ;
12532 DMA_MODULE_ID index ) ;
12556 DMA_MODULE_ID index ) ;
12581 DMA_MODULE_ID index ) ;
12605 DMA_MODULE_ID index ) ;
12629 DMA_MODULE_ID index ) ;
12655 DMA_MODULE_ID index ) ;
12680 DMA_MODULE_ID index ) ;
12704 DMA_MODULE_ID index ) ;
12729 DMA_MODULE_ID index ) ;
12752 DMA_MODULE_ID index ) ;
12775 DMA_MODULE_ID index ) ;
12798 DMA_MODULE_ID index ) ;
12821 DMA_MODULE_ID index ) ;
12846 DMA_MODULE_ID index ) ;
12871 DMA_MODULE_ID index ) ;
12895 DMA_MODULE_ID index ) ;
12920 DMA_MODULE_ID index ) ;
12944 DMA_MODULE_ID index ) ;
12968 DMA_MODULE_ID index ) ;
12991 DMA_MODULE_ID index ) ;
13014 DMA_MODULE_ID index ) ;
13038 DMA_MODULE_ID index ) ;
13062 DMA_MODULE_ID index ) ;
13086 DMA_MODULE_ID index ) ;
13113 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13126 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13139 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13169 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13343 DMA_CRC_TYPE type ;
13349 uint8_t polyLength ;
13352 DMA_CRC_BIT_ORDER bitOrder ;
13355 DMA_CRC_BYTE_ORDER byteOrder ;
13365 uint32_t xorBitMask ;
13490 SYS_MODULE_OBJ
object ,
13491 DMA_CHANNEL activeChannel ) ;
13494 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13539 uintptr_t contextHandle ) ;
13585 const SYS_MODULE_INIT *
const init ) ;
13636 DMA_CHANNEL channel ) ;
13722 DMA_TRIGGER_SOURCE eventSrc ) ;
13800 DMA_PATTERN_LENGTH length ,
13802 uint8_t ignorePattern ) ;
14055 const void * srcAddr ,
14057 const void * destAddr ,
14059 size_t cellSize ) ;
14156 const void * srcAddr ,
14158 const void * destAddr ,
14160 size_t cellSize ) ;
14356 const uintptr_t contextHandle ) ;
14652 DMA_TRIGGER_SOURCE eventSrc ) ;
14831 SYS_MODULE_OBJ
object ,
14832 DMA_CHANNEL activeChannel ) ;
14842 SYS_MODULE_OBJ
object ) ;
14852 SYS_MODULE_OBJ
object ,
14853 DMA_CHANNEL activeChannel ) ;
14880 #define DRV_USART_INDEX_0 0 14881 #define DRV_USART_INDEX_1 1 14882 #define DRV_USART_INDEX_2 2 14883 #define DRV_USART_INDEX_3 3 14884 #define DRV_USART_INDEX_4 4 14885 #define DRV_USART_INDEX_5 5 14899 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14910 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14921 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14955 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15106 uintptr_t context ) ;
15154 USART_HANDSHAKE_MODE_FLOW_CONTROL
15158 USART_HANDSHAKE_MODE_SIMPLEX
15320 } AddressedModeInit ;
15345 = USART_ERROR_PARITY
15350 = USART_ERROR_FRAMING
15355 = USART_ERROR_RECEIVER_OVERRUN
15437 SYS_MODULE_INIT moduleInit ;
15441 USART_MODULE_ID usartID ;
15459 uint32_t brgClock ;
15475 USART_OPERATION_MODE linesEnable ;
15479 INT_SOURCE interruptTransmit ;
15483 INT_SOURCE interruptReceive ;
15487 INT_SOURCE interruptError ;
15492 unsigned int queueSizeReceive ;
15497 unsigned int queueSizeTransmit ;
15501 DMA_CHANNEL dmaChannelTransmit ;
15505 DMA_CHANNEL dmaChannelReceive ;
15509 INT_SOURCE dmaInterruptTransmit ;
15513 INT_SOURCE dmaInterruptReceive ;
15597 const SYS_MODULE_INDEX index ,
15598 const SYS_MODULE_INIT *
const init ) ;
15636 SYS_MODULE_OBJ
object ) ;
15674 SYS_MODULE_OBJ
object ) ;
15715 SYS_MODULE_OBJ
object ) ;
15756 SYS_MODULE_OBJ
object ) ;
15797 SYS_MODULE_OBJ
object ) ;
15876 const SYS_MODULE_INDEX index ,
16060 const size_t size ) ;
16253 const size_t size ) ;
16341 const uintptr_t context ) ;
16608 const size_t numbytes ) ;
16676 const size_t numbytes ) ;
16813 const uint8_t byte ) ;
17031 const SYS_MODULE_INDEX index ,
17084 const SYS_MODULE_INDEX index ,
17133 const SYS_MODULE_INDEX index ,
17348 #ifndef _DRV_USART_FEATURE_MAPPING_H 17349 #define _DRV_USART_FEATURE_MAPPING_H 17358 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17359 #define _DRV_USART_InterruptSourceEnable( source ) 17360 #define _DRV_USART_InterruptSourceDisable( source ) false 17361 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17362 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17363 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17364 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17365 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17368 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17377 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17378 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17379 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17380 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17381 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17394 #include "system/clk/sys_clk.h" 17395 #include "system/int/sys_int.h" 17433 #ifndef _SYS_DEBUG_H 17434 #define _SYS_DEBUG_H 17435 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17438 #define SYS_DEBUG_BUFFER_DMA_READY 17488 #define SYS_DEBUG_INDEX_0 0 17504 SYS_MODULE_INIT moduleInit ;
17508 SYS_MODULE_INDEX consoleIndex ;
17556 const SYS_MODULE_INDEX index ,
17557 const SYS_MODULE_INIT *
const init ) ;
17597 SYS_MODULE_OBJ
object ,
17598 const SYS_MODULE_INIT *
const init ) ;
17628 SYS_MODULE_OBJ
object ) ;
17661 SYS_MODULE_OBJ
object ) ;
17705 SYS_MODULE_OBJ
object ) ;
17748 const char * message ) ;
17798 const char * format ,
17888 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17932 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17975 #define SYS_MESSAGE( message ) 18008 #define SYS_DEBUG_MESSAGE( level , message ) 18055 #define SYS_PRINT( fmt ,... ) 18103 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18128 #define SYS_DEBUG_BreakPoint( ) 18137 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18138 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18139 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18156 #define _DRV_USART_RX_DEPTH 9 18222 const SYS_MODULE_INDEX index ,
18247 const uint8_t byte ) ;
18318 #ifndef _SYS_PORTS_H 18319 #define _SYS_PORTS_H 18358 #ifndef _SYS_PORTS_DEFINITIONS_H 18359 #define _SYS_PORTS_DEFINITIONS_H 18365 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18366 #include "system/common/sys_common.h" 18367 #include "system/common/sys_module.h" 18404 #ifndef _PLIB_PORTS_H 18405 #define _PLIB_PORTS_H 18406 #include <stdint.h> 18407 #include <stddef.h> 18472 #ifndef _PLIB_PORTS_PROCESSOR_H 18473 #define _PLIB_PORTS_PROCESSOR_H 18474 #error "Can't find header" 18524 PORTS_MODULE_ID index ,
18525 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18526 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18569 PORTS_MODULE_ID index ,
18570 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18571 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18606 PORTS_MODULE_ID index ,
18607 PORTS_ANALOG_PIN pin ,
18608 PORTS_PIN_MODE mode ) ;
18648 PORTS_MODULE_ID index ,
18649 PORTS_CHANNEL channel ,
18650 PORTS_BIT_POS bitPos ,
18651 PORTS_PIN_MODE mode ) ;
18686 PORTS_MODULE_ID index ,
18687 PORTS_CHANNEL channel ,
18688 PORTS_BIT_POS bitPos ) ;
18722 PORTS_MODULE_ID index ,
18723 PORTS_CHANNEL channel ,
18724 PORTS_BIT_POS bitPos ) ;
18761 PORTS_MODULE_ID index ,
18762 PORTS_CHANNEL channel ,
18763 PORTS_BIT_POS bitPos ) ;
18804 PORTS_MODULE_ID index ,
18805 PORTS_CHANNEL channel ,
18806 PORTS_BIT_POS bitPos ) ;
18845 PORTS_MODULE_ID index ,
18846 PORTS_CHANNEL channel ,
18847 PORTS_BIT_POS bitPos ) ;
18885 PORTS_MODULE_ID index ,
18886 PORTS_CHANNEL channel ,
18887 PORTS_BIT_POS bitPos ) ;
18922 PORTS_MODULE_ID index ,
18923 PORTS_CHANNEL channel ) ;
18958 PORTS_MODULE_ID index ,
18959 PORTS_CHANNEL channel ) ;
18996 PORTS_MODULE_ID index ,
18997 PORTS_CHANNEL channel ) ;
19034 PORTS_MODULE_ID index ,
19035 PORTS_CHANNEL channel ) ;
19072 PORTS_MODULE_ID index ,
19073 PORTS_CHANNEL channel ,
19074 PORTS_BIT_POS bitPos ) ;
19111 PORTS_MODULE_ID index ,
19112 PORTS_CHANNEL channel ,
19113 PORTS_BIT_POS bitPos ) ;
19151 PORTS_MODULE_ID index ,
19152 PORTS_CHANNEL channel ,
19153 PORTS_BIT_POS bitPos ) ;
19190 PORTS_MODULE_ID index ,
19191 PORTS_CHANNEL channel ,
19192 PORTS_BIT_POS bitPos ,
19227 PORTS_MODULE_ID index ,
19228 PORTS_CHANNEL channel ,
19229 PORTS_BIT_POS bitPos ) ;
19263 PORTS_MODULE_ID index ,
19264 PORTS_CHANNEL channel ,
19265 PORTS_BIT_POS bitPos ) ;
19299 PORTS_MODULE_ID index ,
19300 PORTS_CHANNEL channel ,
19301 PORTS_BIT_POS bitPos ) ;
19336 PORTS_MODULE_ID index ,
19337 PORTS_CHANNEL channel ,
19338 PORTS_BIT_POS bitPos ) ;
19373 PORTS_MODULE_ID index ,
19374 PORTS_CHANNEL channel ,
19375 PORTS_BIT_POS bitPos ) ;
19409 PORTS_MODULE_ID index ,
19410 PORTS_CHANNEL channel ,
19411 PORTS_BIT_POS bitPos ) ;
19445 PORTS_MODULE_ID index ,
19446 PORTS_CHANNEL channel ,
19447 PORTS_BIT_POS bitPos ) ;
19485 PORTS_MODULE_ID index ,
19486 PORTS_CHANNEL channel ) ;
19520 PORTS_MODULE_ID index ,
19521 PORTS_CHANNEL channel ) ;
19555 PORTS_MODULE_ID index ,
19556 PORTS_CHANNEL channel ,
19599 PORTS_MODULE_ID index ,
19600 PORTS_CHANNEL channel ,
19636 PORTS_MODULE_ID index ,
19637 PORTS_CHANNEL channel ,
19672 PORTS_MODULE_ID index ,
19673 PORTS_CHANNEL channel ,
19709 PORTS_MODULE_ID index ,
19710 PORTS_CHANNEL channel ,
19745 PORTS_MODULE_ID index ,
19746 PORTS_CHANNEL channel ,
19779 PORTS_MODULE_ID index ,
19780 PORTS_CHANNEL channel ) ;
19814 PORTS_MODULE_ID index ,
19815 PORTS_CHANNEL channel ,
19851 PORTS_MODULE_ID index ,
19852 PORTS_CHANNEL channel ,
19898 PORTS_MODULE_ID index ,
19899 PORTS_CHANNEL channel ,
19901 PORTS_PIN_MODE mode ) ;
19943 PORTS_MODULE_ID index ,
19944 PORTS_CHANNEL channel ,
19987 PORTS_MODULE_ID index ,
19988 PORTS_CHANNEL channel ,
20028 PORTS_MODULE_ID index ,
20029 PORTS_CHANNEL channel ,
20069 PORTS_MODULE_ID index ,
20070 PORTS_CHANNEL channel ,
20114 PORTS_MODULE_ID index ,
20115 PORTS_CHANNEL channel ,
20159 PORTS_MODULE_ID index ,
20160 PORTS_CHANNEL channel ,
20206 PORTS_MODULE_ID index ,
20207 PORTS_AN_PIN anPins ,
20208 PORTS_PIN_MODE mode ) ;
20251 PORTS_MODULE_ID index ,
20252 PORTS_CN_PIN cnPins ) ;
20296 PORTS_MODULE_ID index ,
20297 PORTS_CN_PIN cnPins ) ;
20340 PORTS_MODULE_ID index ,
20341 PORTS_CN_PIN cnPins ) ;
20384 PORTS_MODULE_ID index ,
20385 PORTS_CN_PIN cnPins ) ;
20419 PORTS_MODULE_ID index ) ;
20452 PORTS_MODULE_ID index ) ;
20488 PORTS_MODULE_ID index ,
20489 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20525 PORTS_MODULE_ID index ,
20526 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20563 PORTS_MODULE_ID index ) ;
20597 PORTS_MODULE_ID index ) ;
20633 PORTS_MODULE_ID index ,
20634 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20670 PORTS_MODULE_ID index ,
20671 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20716 PORTS_MODULE_ID index ,
20717 PORTS_CHANNEL channel ,
20719 PORTS_PIN_SLEW_RATE slewRate ) ;
20756 PORTS_PIN_SLEW_RATE
20758 PORTS_MODULE_ID index ,
20759 PORTS_CHANNEL channel ,
20760 PORTS_BIT_POS bitPos ) ;
20799 PORTS_MODULE_ID index ,
20800 PORTS_CHANNEL channel ,
20801 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20834 PORTS_CHANGE_NOTICE_METHOD
20836 PORTS_MODULE_ID index ,
20837 PORTS_CHANNEL channel ) ;
20885 PORTS_MODULE_ID index ,
20886 PORTS_CHANNEL channel ,
20936 PORTS_MODULE_ID index ,
20937 PORTS_CHANNEL channel ,
20985 PORTS_MODULE_ID index ,
20986 PORTS_CHANNEL channel ,
20987 PORTS_BIT_POS bitPos ,
20988 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21031 PORTS_MODULE_ID index ,
21032 PORTS_CHANNEL channel ,
21033 PORTS_BIT_POS bitPos ) ;
21064 PORTS_MODULE_ID index ) ;
21088 PORTS_MODULE_ID index ) ;
21112 PORTS_MODULE_ID index ) ;
21136 PORTS_MODULE_ID index ) ;
21161 PORTS_MODULE_ID index ) ;
21186 PORTS_MODULE_ID index ) ;
21217 PORTS_MODULE_ID index ) ;
21245 PORTS_MODULE_ID index ) ;
21272 PORTS_MODULE_ID index ) ;
21297 PORTS_MODULE_ID index ) ;
21324 PORTS_MODULE_ID index ) ;
21349 PORTS_MODULE_ID index ) ;
21376 PORTS_MODULE_ID index ) ;
21401 PORTS_MODULE_ID index ) ;
21429 PORTS_MODULE_ID index ) ;
21457 PORTS_MODULE_ID index ) ;
21485 PORTS_MODULE_ID index ) ;
21511 PORTS_MODULE_ID index ) ;
21537 PORTS_MODULE_ID index ) ;
21563 PORTS_MODULE_ID index ) ;
21588 PORTS_MODULE_ID index ) ;
21614 PORTS_MODULE_ID index ) ;
21641 PORTS_MODULE_ID index ) ;
21666 PORTS_MODULE_ID index ) ;
21701 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21702 #define _PLIB_PORTS_COMPATIBILITY_H 21703 #include <stdint.h> 21704 #include <stddef.h> 21739 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21756 #include "system/int/sys_int.h" 21890 PORTS_MODULE_ID index ,
21891 PORTS_CHANNEL channel ) ;
21923 PORTS_MODULE_ID index ,
21924 PORTS_CHANNEL channel ,
21954 PORTS_MODULE_ID index ,
21955 PORTS_CHANNEL channel ) ;
21993 PORTS_MODULE_ID index ,
21994 PORTS_CHANNEL channel ,
22028 PORTS_MODULE_ID index ,
22029 PORTS_CHANNEL channel ,
22066 PORTS_MODULE_ID index ,
22068 PORTS_CHANNEL channel ,
22098 PORTS_MODULE_ID index ,
22099 PORTS_CHANNEL channel ) ;
22130 PORTS_MODULE_ID index ,
22131 PORTS_CHANNEL channel ,
22163 PORTS_MODULE_ID index ,
22164 PORTS_CHANNEL channel ,
22196 PORTS_MODULE_ID index ,
22197 PORTS_CHANNEL channel ,
22231 PORTS_MODULE_ID index ,
22232 PORTS_CHANNEL channel ) ;
22272 PORTS_MODULE_ID index ,
22273 PORTS_REMAP_INPUT_FUNCTION
function ,
22274 PORTS_REMAP_INPUT_PIN remapPin ) ;
22309 PORTS_MODULE_ID index ,
22310 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22311 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22344 PORTS_MODULE_ID index ) ;
22372 PORTS_MODULE_ID index ) ;
22406 PORTS_MODULE_ID index ,
22407 PORTS_CHANGE_NOTICE_PIN pinNum ,
22439 PORTS_MODULE_ID index ,
22440 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22469 PORTS_MODULE_ID index ) ;
22498 PORTS_MODULE_ID index ) ;
22529 PORTS_MODULE_ID index ,
22530 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22561 PORTS_MODULE_ID index ,
22562 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22601 PORTS_MODULE_ID index ,
22602 PORTS_ANALOG_PIN pin ,
22603 PORTS_PIN_MODE mode ) ;
22640 PORTS_MODULE_ID index ,
22641 PORTS_CHANNEL channel ,
22642 PORTS_BIT_POS bitPos ,
22677 PORTS_MODULE_ID index ,
22678 PORTS_CHANNEL channel ,
22679 PORTS_BIT_POS bitPos ) ;
22712 PORTS_MODULE_ID index ,
22713 PORTS_CHANNEL channel ,
22714 PORTS_BIT_POS bitPos ) ;
22747 PORTS_MODULE_ID index ,
22748 PORTS_CHANNEL channel ,
22749 PORTS_BIT_POS bitPos ) ;
22782 PORTS_MODULE_ID index ,
22783 PORTS_CHANNEL channel ,
22784 PORTS_BIT_POS bitPos ) ;
22817 PORTS_MODULE_ID index ,
22818 PORTS_CHANNEL channel ,
22819 PORTS_BIT_POS bitPos ) ;
22856 PORTS_MODULE_ID index ,
22858 PORTS_CHANNEL channel ,
22859 PORTS_BIT_POS bitPos ) ;
22892 PORTS_MODULE_ID index ,
22893 PORTS_CHANNEL channel ,
22894 PORTS_BIT_POS bitPos ) ;
22927 PORTS_MODULE_ID index ,
22928 PORTS_CHANNEL channel ,
22929 PORTS_BIT_POS bitPos ) ;
22962 PORTS_MODULE_ID index ,
22963 PORTS_CHANNEL channel ,
22964 PORTS_BIT_POS bitPos ) ;
22997 PORTS_MODULE_ID index ,
22998 PORTS_CHANNEL channel ,
22999 PORTS_BIT_POS bitPos ) ;
23032 PORTS_MODULE_ID index ,
23033 PORTS_CHANNEL channel ,
23034 PORTS_BIT_POS bitPos ) ;
23067 PORTS_MODULE_ID index ,
23068 PORTS_CHANNEL channel ,
23069 PORTS_BIT_POS bitPos ) ;
23102 PORTS_MODULE_ID index ,
23103 PORTS_CHANNEL channel ,
23104 PORTS_BIT_POS bitPos ,
23187 #ifndef _DRV_SPI_DEFINITIONS_H 23188 #define _DRV_SPI_DEFINITIONS_H 23194 #include <stdint.h> 23195 #include <stdbool.h> 23196 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23197 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23233 #ifndef _PLIB_SPI_H 23234 #define _PLIB_SPI_H 23268 #ifndef _PLIB_SPI_PROCESSOR_H 23269 #define _PLIB_SPI_PROCESSOR_H 23270 #error "Can't find header" 23315 SPI_MODULE_ID index ) ;
23345 SPI_MODULE_ID index ) ;
23377 SPI_MODULE_ID index ) ;
23409 SPI_MODULE_ID index ) ;
23443 SPI_MODULE_ID index ) ;
23473 SPI_MODULE_ID index ) ;
23510 SPI_MODULE_ID index ) ;
23549 SPI_MODULE_ID index ) ;
23579 SPI_MODULE_ID index ,
23610 SPI_MODULE_ID index ,
23644 SPI_MODULE_ID index ,
23645 SPI_COMMUNICATION_WIDTH width ) ;
23680 SPI_MODULE_ID index ,
23681 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23713 SPI_MODULE_ID index ,
23714 SPI_INPUT_SAMPLING_PHASE phase ) ;
23746 SPI_MODULE_ID index ,
23747 SPI_OUTPUT_DATA_PHASE phase ) ;
23778 SPI_MODULE_ID index ,
23779 SPI_CLOCK_POLARITY polarity ) ;
23809 SPI_MODULE_ID index ) ;
23839 SPI_MODULE_ID index ) ;
23877 SPI_MODULE_ID index ,
23878 uint32_t clockFrequency ,
23879 uint32_t baudRate ) ;
23910 SPI_MODULE_ID index ) ;
23942 SPI_MODULE_ID index ) ;
23975 SPI_MODULE_ID index ) ;
24008 SPI_MODULE_ID index ) ;
24040 SPI_MODULE_ID index ) ;
24070 SPI_MODULE_ID index ) ;
24101 SPI_MODULE_ID index ) ;
24132 SPI_MODULE_ID index ) ;
24163 SPI_MODULE_ID index ) ;
24195 SPI_MODULE_ID index ,
24196 SPI_FIFO_TYPE type ) ;
24228 SPI_MODULE_ID index ) ;
24260 SPI_MODULE_ID index ) ;
24294 SPI_MODULE_ID index ,
24295 SPI_FIFO_INTERRUPT mode ) ;
24325 SPI_MODULE_ID index ) ;
24355 SPI_MODULE_ID index ) ;
24387 SPI_MODULE_ID index ,
24388 SPI_FRAME_PULSE_DIRECTION direction ) ;
24421 SPI_MODULE_ID index ,
24422 SPI_FRAME_PULSE_POLARITY polarity ) ;
24455 SPI_MODULE_ID index ,
24456 SPI_FRAME_PULSE_EDGE edge ) ;
24489 SPI_MODULE_ID index ,
24490 SPI_FRAME_PULSE_WIDTH width ) ;
24524 SPI_MODULE_ID index ,
24525 SPI_FRAME_SYNC_PULSE pulse ) ;
24557 SPI_MODULE_ID index ) ;
24587 SPI_MODULE_ID index ) ;
24619 SPI_MODULE_ID index ) ;
24649 SPI_MODULE_ID index ) ;
24679 SPI_MODULE_ID index ) ;
24709 SPI_MODULE_ID index ) ;
24740 SPI_MODULE_ID index ,
24772 SPI_MODULE_ID index ,
24804 SPI_MODULE_ID index ,
24827 SPI_MODULE_ID index ) ;
24858 SPI_MODULE_ID index ,
24859 SPI_BAUD_RATE_CLOCK type ) ;
24891 SPI_MODULE_ID index ,
24892 SPI_ERROR_INTERRUPT error ) ;
24924 SPI_MODULE_ID index ,
24925 SPI_ERROR_INTERRUPT error ) ;
24956 SPI_MODULE_ID index ,
24957 SPI_AUDIO_ERROR error ) ;
24988 SPI_MODULE_ID index ,
24989 SPI_AUDIO_ERROR error ) ;
25019 SPI_MODULE_ID index ) ;
25049 SPI_MODULE_ID index ) ;
25081 SPI_MODULE_ID index ,
25082 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25114 SPI_MODULE_ID index ,
25115 SPI_AUDIO_PROTOCOL mode ) ;
25148 SPI_MODULE_ID index ) ;
25174 SPI_MODULE_ID index ) ;
25200 SPI_MODULE_ID index ) ;
25225 SPI_MODULE_ID index ) ;
25250 SPI_MODULE_ID index ) ;
25275 SPI_MODULE_ID index ) ;
25301 SPI_MODULE_ID index ) ;
25326 SPI_MODULE_ID index ) ;
25351 SPI_MODULE_ID index ) ;
25376 SPI_MODULE_ID index ) ;
25401 SPI_MODULE_ID index ) ;
25426 SPI_MODULE_ID index ) ;
25452 SPI_MODULE_ID index ) ;
25477 SPI_MODULE_ID index ) ;
25502 SPI_MODULE_ID index ) ;
25527 SPI_MODULE_ID index ) ;
25553 SPI_MODULE_ID index ) ;
25579 SPI_MODULE_ID index ) ;
25605 SPI_MODULE_ID index ) ;
25629 SPI_MODULE_ID index ) ;
25654 SPI_MODULE_ID index ) ;
25679 SPI_MODULE_ID index ) ;
25704 SPI_MODULE_ID index ) ;
25730 SPI_MODULE_ID index ) ;
25755 SPI_MODULE_ID index ) ;
25780 SPI_MODULE_ID index ) ;
25805 SPI_MODULE_ID index ) ;
25830 SPI_MODULE_ID index ) ;
25855 SPI_MODULE_ID index ) ;
25881 SPI_MODULE_ID index ) ;
25908 SPI_MODULE_ID index ) ;
25933 SPI_MODULE_ID index ) ;
25959 SPI_MODULE_ID index ) ;
25985 SPI_MODULE_ID index ) ;
26011 SPI_MODULE_ID index ) ;
26036 SPI_MODULE_ID index ) ;
26061 SPI_MODULE_ID index ) ;
26087 SPI_MODULE_ID index ) ;
26113 SPI_MODULE_ID index ) ;
26125 #include "system/common/sys_common.h" 26126 #include "system/common/sys_module.h" 26127 #include "system/int/sys_int.h" 26128 #include "system/clk/sys_clk.h" 26129 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26167 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26179 #define DRV_SPI_INDEX_0 0 26180 #define DRV_SPI_INDEX_1 1 26181 #define DRV_SPI_INDEX_2 2 26182 #define DRV_SPI_INDEX_3 3 26183 #define DRV_SPI_INDEX_4 4 26184 #define DRV_SPI_INDEX_5 5 26196 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26445 SPI_MODULE_ID
spiId ;
26478 CLK_BUSES_PERIPHERAL
spiClk ;
26638 const SYS_MODULE_INDEX index ,
26639 const SYS_MODULE_INIT *
const init ) ;
26681 SYS_MODULE_OBJ
object ) ;
26730 SYS_MODULE_OBJ
object ) ;
26771 SYS_MODULE_OBJ
object ) ;
26836 const SYS_MODULE_INDEX drvIndex ,
27431 #include "driver/usb/usbhs/drv_usbhs.h" 27432 #include "usb/usb_device.h" 27460 #include <stdint.h> 27480 uint8_t RevNumber ;
27567 SYS_MODULE_OBJ sysTmr ;
27568 SYS_MODULE_OBJ drvTmr0 ;
27569 SYS_MODULE_OBJ drvTmr1 ;
27570 SYS_MODULE_OBJ drvTmr2 ;
27571 SYS_MODULE_OBJ drvTmr3 ;
27572 SYS_MODULE_OBJ drvTmr4 ;
27573 SYS_MODULE_OBJ drvUsart0 ;
27574 SYS_MODULE_OBJ drvPMP0 ;
27576 SYS_MODULE_OBJ spiObjectIdx0 ;
27578 SYS_MODULE_OBJ spiObjectIdx1 ;
27580 SYS_MODULE_OBJ spiObjectIdx2 ;
27581 SYS_MODULE_OBJ drvUSBObject ;
27582 SYS_MODULE_OBJ usbDevObject0 ;
27651 bool spi_write_complete_flag ;
27652 bool spi_sent_flag ;
27653 uint16_t adj [ 1 ] ;
27656 bool new_cont_values_flag ;
27658 uint16_t cont_prev ;
27659 uint16_t cont_new ;
27663 uint16_t update_rate ;
27664 uint16_t rate_time ;
27665 uint16_t update_count ;
27669 uint16_t sensor_offset ;
27671 uint16_t sensor_constant ;
27672 uint16_t max_current ;
27673 uint16_t current_limit ;
27674 uint16_t upper_current_limit ;
27675 uint8_t over_current_count ;
27676 bool new_current_values_flag ;
27677 bool new_voltage_values_flag ;
27678 bool overcurrent_flag ;
27679 bool overvoltage_flag ;
27778 #include <stdint.h> 27779 #include <stdbool.h> 27819 uint16_t hvps_cont ;
27820 uint16_t wl_cps_i ;
27821 uint16_t wl_cps_v ;
27822 uint16_t wl_sps_i_cf ;
27823 uint16_t wl_sps_i ;
27892 #include <stdbool.h> 27893 #include "../system_config.h" 27894 #include "../system_definitions.h" 27910 #define ManHalfUpper 11800U 27911 #define ManHalfLower 2000U 27912 #define ManFullUpper 20000U 27913 #define ManFullLower 11801U 27914 #define NoManBits 32U 27915 #define HalfBit 0x12U 27916 #define FullBit 0x10U 27917 #define SizeOfBiasLUT 48U 27997 uint16_t preamble [ 5 ] ;
27998 uint16_t time [ 96 ] ;
27999 uint8_t level [ 96 ] ;
28000 uint8_t ans [ 32U + 2 ] ;
28001 uint8_t msg [ 4 ] ;
28002 uint8_t cnt_preamble ;
28003 uint8_t trynumber ;
28004 bool process_complete_flag ;
28005 bool spi_write_complete_flag ;
28006 bool spi_sent_flag ;
28007 uint8_t timer_count ;
28008 uint8_t timer_complete ;
28012 bool manual_bias_flag ;
28035 uint16_t adj [ 1 ] ;
28036 uint16_t dac_a_setting ;
28037 uint16_t dac_b_setting ;
28429 #include "../system_config.h" 28430 #include "../system_definitions.h" 28431 #include <stdbool.h> 28440 #define NEGATIVE_OFFSET 0x02U 28441 #define POS_HIGH_OFFSET 0x01U 28442 #define POS_LOW_OFFSET 0x03U 28443 #define DEFAULT_OFFSET 0x04U 28444 #define I_ARRAY_SIZE 50U 28491 uint16_t voltage_limit ;
28492 uint16_t upper_voltage_limit ;
28493 uint16_t volt_count ;
28495 uint16_t max_current ;
28496 uint16_t current_limit ;
28497 uint16_t upper_current_limit ;
28498 uint8_t over_current_count ;
28499 uint8_t array_sum_count ;
28500 uint8_t array_count ;
28502 int16_t i_array [ 50U ] ;
28504 bool new_current_values_flag ;
28505 bool new_voltage_values_flag ;
28506 bool overcurrent_flag ;
28507 bool overvoltage_flag ;
28508 uint16_t sensor_offset ;
28509 uint16_t sensor_constant ;
28510 bool sensor_offset_tick ;
28511 uint16_t v_array [ 50 ] ;
28512 uint16_t v_array_count ;
28518 uint8_t overvoltage_count ;
28649 #include <stdbool.h> 28650 #include <stdint.h> 28682 uint8_t bitposn ) ;
28708 uint8_t bitposn ) ;
28812 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28836 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 0)));
28872 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 4)));
28902 4096.0F ) * ( 1.3243F /
28904 * 1000.0F * .650F ) ;
29382 #define qqqbranches 160 29383 #define QQQMAXMCDCSIZE 2 29387 #define ldra_sscanf 29403 #undef qqnull_params 29404 #define qqnull_params void 29406 #define qqzzidfield 1 29412 #define QQQFIXEDSIZE 29432 qqcptr = qqscan_str;
29434 while (qqcptr[0] ==
' ')
29440 if (qqcptr[0] ==
'-')
29446 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
29448 qqvalue = 10 * qqvalue;
29449 qqvalue = qqvalue + (qqcptr[0] -
'0');
29452 qqvalue = qqisign * qqvalue;
29478 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
29479 ldra_port_write (&ldra_buffer[0]);
29487 ldra_port_write(s);
29495 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
29496 ldra_port_write (&ldra_buffer[0]);
29504 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
29505 ldra_port_write (&ldra_buffer[0]);
29513 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
29514 ldra_port_write (&ldra_buffer[0]);
29633 static int branches_printed = 0;
29637 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
29638 ldra_port_write (&ldra_buffer[0]);
29639 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
29640 ldra_port_write (&ldra_buffer[0]);
29642 branches_printed += 8;
29662 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 29663 #define LASTELEMENT 29664 #include "hvps_61zbelem.def" void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
uint32_t DRV_TMR1_PeriodValueGet(void)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
bool DRV_USART0_TransmitBufferIsFull(void)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
SYS_DMA_CHANNEL_IGNORE_MATCH
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
static SYS_STATUS DRV_TMR2_Status(void)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
bool DRV_SPIn_TransmitterBufferIsFull(void)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
uint32_t DRV_TMR3_PeriodValueGet(void)
static SYS_STATUS DRV_TMR3_Status(void)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
static unsigned char qqqzzglobflag
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
uint32_t DRV_TMR1_CounterValueGet(void)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
static float32_t Calc_Fsk_Scaling(void)
void DRV_USART_Close(const DRV_HANDLE handle)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
static void qqoutput0(FILEPOINT char *s)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
bool DRV_IC0_BufferIsEmpty(void)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART0_TasksError(void)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
uint8_t DRV_PMP0_Read(void)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
static void DRV_TMR0_DeInitialize(void)
void DRV_TMR_Close(DRV_HANDLE handle)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
#define DRV_IC_Open(drvIndex, intent)
static void Flush_Buffer_Manchester(void)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
uint32_t SYS_DMA_ChannelCRCGet(void)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
bool DRV_TMR3_Start(void)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
void DRV_USART0_TasksReceive(void)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
void DRV_TMR0_StopInIdleEnable(void)
static void DRV_TMR1_Close(void)
void Prepare_Return_B(uint8_t byt [])
DRV_USART_LINE_CONTROL_SET_RESULT
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
void DRV_TMR3_CounterValueSet(uint32_t value)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
uint32_t DRV_TMR4_PeriodValueGet(void)
void DRV_TMR1_StopInIdleEnable(void)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t DRV_USART0_ReadByte(void)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
static void Decode_Manchester(void)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
DRV_USART_BAUD_SET_RESULT
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void DRV_TMR0_CounterValueSet(uint32_t value)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool spi_write_complete_flag
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_USART0_WriteByte(const uint8_t byte)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_TMR2_CounterClear(void)
void Clear_Status(uint8_t bitposn)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
uint8_t jobQueueReserveSize
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
SYS_MODULE_INIT moduleInit
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
void DRV_TMR1_Initialize(void)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static int qqqisinitialised
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void SYS_DEBUG_Message(const char *message)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void DRV_PMP0_Write(uint8_t data)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
static void qqoutput2(FILEPOINT char *s, int i, int j)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void DRV_TMR4_CounterValueSet(uint32_t value)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
void DRV_TMR0_Initialize(void)
INT_SOURCE txInterruptSource
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
static void DRV_TMR2_Open(void)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
uint32_t DRV_TMR3_CounterValueGet(void)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void DRV_TMR1_CounterValueSet(uint32_t value)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR_Stop(DRV_HANDLE handle)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
static int qqqqbmselwidth
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
void DRV_TMR4_CounterClear(void)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
void DRV_TMR2_StopInIdleDisable(void)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
static void DRV_TMR1_DeInitialize(void)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_ADC_Initialize(void)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
void DRV_TMR3_StopInIdleEnable(void)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
static void DRV_TMR3_DeInitialize(void)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
DRV_USART_TRANSFER_STATUS
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static int hvps_61zscanf(char *qqscan_str)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
SPI_FRAME_PULSE_WIDTH framePulseWidth
static int hvps_61zqqzqz(qqnull_params)
static void DRV_TMR3_Close(void)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
static void Package_Manchester(void)
uintptr_t DRV_SPI_BUFFER_HANDLE
static void DRV_TMR0_Close(void)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_DMA_Suspend(void)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
uint32_t DRV_TMR0_PeriodValueGet(void)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SYS_ERROR_LEVEL gblErrLvl
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void APP_Initialize(void)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
void DRV_ADC_DeInitialize(void)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void Set_WL_SPS_CurrentLimit(uint16_t value)
void DRV_TMR1_CounterClear(void)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void DRV_USART0_TasksTransmit(void)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
static void DRV_TMR0_Open(void)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
void SYS_PORTS_Initialize()
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
DRV_SPI_BUFFER_TYPE bufferType
uint32_t DRV_TMR4_CounterValueGet(void)
bool DRV_TMR0_Start(void)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
void Set_Bias(uint8_t value)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
static void qqqbitmapreset(qqnull_params)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
static void SPI_4_EventHandler(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool DRV_TMR2_Start(void)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
static void DRV_TMR4_Tasks(void)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
static void DRV_TMR3_Tasks(void)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
void Set_Status(uint8_t bitposn)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
void PLIB_USART_Enable(USART_MODULE_ID index)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
static void qqqupload(qqnull_params)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR3_CounterClear(void)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void DRV_TMR2_Initialize(void)
void DRV_USART0_Close(void)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void DRV_TMR4_Initialize(void)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
static void DRV_TMR1_Tasks(void)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
struct _DRV_SPI_INIT DRV_SPI_INIT
void qqqtotalupload(void)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
static void DRV_TMR4_Open(void)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
uint16_t DRV_IC0_Capture16BitDataRead(void)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void DRV_USART0_Deinitialize(void)
DRV_SPI_BUFFER_HANDLE bufferHandle2
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
uintptr_t DRV_USART_BUFFER_HANDLE
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
void DRV_TMR3_Initialize(void)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
void DRV_TMR3_StopInIdleDisable(void)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
uintptr_t DRV_USART_BUFFER_HANDLE
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
void DRV_TMR4_StopInIdleEnable(void)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
static void DRV_TMR4_DeInitialize(void)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
CLK_BUSES_PERIPHERAL spiClk
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
void Set_HVPS_Ramp_Rate(uint16_t value)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool SYS_DMA_IsBusy(void)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
SPI_COMMUNICATION_WIDTH commWidth
uint32_t DRV_TMR2_CounterValueGet(void)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
static void DRV_TMR2_Close(void)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR0_StopInIdleDisable(void)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
static void Test_Manchester(void)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
#define DRV_IC_Close(handle)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint16_t upper_voltage_limit
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
bool new_current_values_flag
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
void Calc_Auto_Bias(void)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void DRV_TMR0_PeriodValueSet(uint32_t value)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR4_PeriodValueSet(uint32_t value)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
static bool Check_Manchester(void)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
void DRV_TMR0_CounterClear(void)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
void DRV_TMR1_StopInIdleDisable(void)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
static void Init_Manchester(void)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
void SET_WL_SPS_IOffset(uint8_t mode)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
void DRV_IC_Stop(DRV_HANDLE handle)
static int hvps_61zqendz(int qqqi)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void(* ldra_void_function)()
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
static SYS_STATUS DRV_TMR0_Status(void)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
uint32_t DRV_IC0_Capture32BitDataRead(void)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
void DRV_ADC1_Close(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
bool new_cont_values_flag
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_PMP0_ModeConfig(void)
void DRV_TMR1_PeriodValueSet(uint32_t value)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_DMA_CHANNEL_CHAIN_PRIO
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
static void DRV_TMR4_Close(void)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
static SYS_STATUS DRV_TMR4_Status(void)
void DRV_TMR3_PeriodValueSet(uint32_t value)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
static void DRV_TMR1_Open(void)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static SYS_STATUS DRV_TMR1_Status(void)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
void DRV_TMR4_StopInIdleDisable(void)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
SPI_AUDIO_PROTOCOL audioProtocolMode
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
DRV_SPI_CLOCK_MODE clockMode
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
static int hvps_61zqzqzq(int qqqi)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR0_Tasks(void)
static void DRV_TMR2_Tasks(void)
void DRV_ADC0_Close(void)
static void DRV_TMR2_DeInitialize(void)
bool DRV_SPIn_ReceiverBufferIsFull(void)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
uintptr_t SYS_DMA_CHANNEL_HANDLE
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
static void qqoutput(FILEPOINT char *s, int i)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR2_CounterValueSet(uint32_t value)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DEBUG_Print(const char *format,...)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
ldra_void_function qqqaccumupload[QQQnumfil]
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
INT_SOURCE rxInterruptSource
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
bool DRV_TMR4_Start(void)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
bool DRV_TMR1_Start(void)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
static struct bitmapstruct_t bitmapstruct
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
void DRV_PMP0_Initialize(void)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
static void DRV_TMR3_Open(void)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
INT_SOURCE errInterruptSource
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
ldra_void_function qqqaccumreset[QQQnumfil]
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_Disable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE bufferHandle
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
static int qqqstructzzopen
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR2_PeriodValueSet(uint32_t value)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
DRV_SPI_TASK_MODE taskMode
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
static void MAN_PROCESS_Tasks(void)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
uint32_t DRV_TMR2_PeriodValueGet(void)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
SYS_STATUS DRV_USART0_Status(void)
uint32_t DRV_TMR0_CounterValueGet(void)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
static void qqqqinitialise(int ii)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
static HVPS_STATES H_STATES
uint8_t over_current_count
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_Resume(void)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
bool DRV_TMR_Start(DRV_HANDLE handle)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR2_StopInIdleEnable(void)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
void DRV_IC0_Initialize(void)
SPI_FRAME_SYNC_PULSE frameSyncPulse
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)